In a fabrication of IC designs, particularly a fabrication of IC designs using SADP technology, vias are typically placed to connect layers, for instance ‘metal 1’ (M1) and ‘metal 2’ (M2) layers. Such, vias are frequently sized and positioned early in a design process to efficiently utilize space on an IC design and to obtain adequate performance, reliability, and manufacturability of the resulting device. Additional vias may be inserted, at later steps in the design process (e.g., after placement and routing (P&R), after decomposition) to improve performance, reliability, and manufacturability of the resulting device. However, to ensure a manufacturability of a resulting device, traditional processes require complex two-dimensional design rule checks (DRCs) that slow down the runtime of standard IC design tools, such as DRC engines and automated routers, which increases the overall design cycle time. Furthermore, traditional DRCs may be color dependent and thus require decomposition information such as whether a feature is a mandrel or non-mandrel metal and tip-to-tip, side-to-tip, and side-to-side distances.
A need therefore exists for methodology and an apparatus enabling an insertion of vias that ensures a manufacturability of a resulting device without a complex two-dimensional DRC and is color independent.